RRAM variability and its mitigation schemes

Emerging technologies such as RRAMs are attracting significant attention due to their tempting characteristics such as high scalability, CMOS compatibility and non-volatility to replace the current conventional memories. However, critical causes of hardware reliability failures, such as process variation due to their nano-scale structure have gained considerable importance for acceptable memory yields. Such vulnerabilities make it essential to investigate new robust design strategies at the circuit system level. In this paper we have analyzed the RRAM variability phenomenon, its impact and variation tolerant techniques at the circuit level. Finally a variation-monitoring circuit is presented that discerns the reliable memory cells affected by process variability.Peer ReviewedPostprint (author's final draft

A circuit-level SPICE modeling strategy for the simulation of behavioral variability in ReRAM

© 2022 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.The intrinsic behavioral variability in resistive switching devices (also known as 'memristors' or 'ReRAM devices') can be a reliability limiting factor or an opportunity for applications where randomness of resistance switching is essential, such as hardware security and stochastic computing. The realistic assessment of ReRAM-based circuits & systems towards practical exploitation requires variability-aware ReRAM modeling. In this context, here we present a versatile, circuit-level implementation strategy to incorporate cycle-to-cycle (C2C) variability to the ReRAM model parameters in SPICE simulations. We evaluated the proposed approach with threshold-based models of a voltage-controlled bipolar ReRAM device and managed to reproduce the main features observed in experimental curves for different pulsed voltage inputs. With key upgrades, compared to previous approaches found in the literature, our strategy enables the enhancement of any ReRAM device model towards the exploration of new ways to make the most of the C2C ReRAM variability, and to test the robustness of any designed circuits & systems against ReRAM variability.Supported by the Chilean research grants ANID-Basal FB0008 and FONDECYT Regular 1221747, and by the Spanish MCIN/AEI/10.13039/501100011033 grant PID2019-103869RB-C33.Peer ReviewedPostprint (author's final draft

Implementation of a 5x5 trits multiplier in a quasi-adiabatic ternary CMOS logic

© 1997 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.Adiabatic switching is one technique to design low power digital IC. In order to diminish its expensive silicon area requirements an adiabatic ternary logic is proposed. A 5×5 trits (ternary signals) multiplier has been designed and implemented using this logic in a 0.7µm CMOS technology. Results show a satisfactory power saving and a decreasing of the area needed with respect to an adiabatic binary one.Peer ReviewedPostprint (published version

Fault-tolerant nanoscale architecture based on linear threshold gates with redundancy

One of the main objectives of the data computing and memory industry is to keep and ever accelerate the increase of component density reached in nowadays integrated circuits in future technologies based on ultimate CMOS and new emerging research devices. The worldwide-accepted predictions with these technologies indicate a remarkable reduction of the components quality, because of the manufacturing process complexity and the erratic behavior of devices, causing a drop in the system reliability if we maintain the same design rules than today. Together with the introduction of new devices, new architectural design paradigms have to be included. Fault tolerant techniques are considered necessary and relevant in this scenario. In this paper we present a Fault-Tolerant Nanoscale architecture based on the implementation of logic systems with averaging cells linear threshold gates (AC-LTG). The sensitivity of the gates in relation with manufacturing and environment deviation is investigated and compared with the well known NAND multiplexing concept, showing that the AC-LTG is a valuable alternative in specific nanoscale conditions.Peer ReviewedPostprint (published version

Experimental study of artificial neural networks using a digital memristor simulator

© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.This paper presents a fully digital implementation of a memristor hardware simulator, as the core of an emulator, based on a behavioral model of voltage-controlled threshold-type bipolar memristors. Compared to other analog solutions, the proposed digital design is compact, easily reconfigurable, demonstrates very good matching with the mathematical model on which it is based, and complies with all the required features for memristor emulators. We validated its functionality using Altera Quartus II and ModelSim tools targeting low-cost yet powerful field programmable gate array (FPGA) families. We tested its suitability for complex memristive circuits as well as its synapse functioning in artificial neural networks (ANNs), implementing examples of associative memory and unsupervised learning of spatio-temporal correlations in parallel input streams using a simplified STDP. We provide the full circuit schematics of all our digital circuit designs and comment on the required hardware resources and their scaling trends, thus presenting a design framework for applications based on our hardware simulator.Peer ReviewedPostprint (author's final draft

Statistical analysis and comparison of 2T and 3T1D e-DRAM minimum energy operation

Bio-medical wearable devices restricted to their small-capacity embedded-battery require energy-efficiency of the highest order. However, minimum-energy point (MEP) at sub-threshold voltages is unattainable with SRAM memory, which fails to hold below 0.3V because of its vanishing noise margins. This paper examines the minimum-energy operation point of 2T and 3T1D e-DRAM gain cells at the 32-nm technology node with different design points: up-sizing transistors, using high- V th transistors, read/write wordline assists; as well as operating conditions (i.e., temperature). First, the e-DRAM cells are evaluated without considering any process variations. Then, a full-factorial statistical analysis of e-DRAM cells is performed in the presence of threshold voltage variations and the effect of upsizing on mean MEP is reported. Finally, it is shown that the product of the read and write lengths provides a knob to tradeoff energy-efficiency for reliable MEP energy operation.Peer ReviewedPostprint (author's final draft

Reliability issues in RRAM ternary memories affected by variability and aging mechanisms

© 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.Resistive switching Random Access Memories (RRAM) are being considered as a promising alternative for conventional memories mainly due to their high speed, scalability, CMOS compatibility, Non-Volatile behavior (NVM), and consequent orientation to low power consumption. Advances in the RRAM technology as well as enhancement of the control of the cells are opening the use of these devices for multi-valued logic. But the cycle-to-cycle variability and the still reduced endurance are becoming serious limitations. This paper analyzes the impact of both mechanisms on 1T1R cells and suggests potential adaptive mechanisms to enlarge its lifetime.Peer ReviewedPostprint (author's final draft

Statistical lifetime analysis of memristive crossbar matrix

Memristors are considered one of the most favorable emerging device alternatives for future memory technologies. They are attracting great attention recently, due to their high scalability and compatibility with CMOS fabrication process. Alongside their benefits, they also face reliability concerns (e.g. manufacturing variability). In this sense our work analyzes key sources of uncertainties in the operation of the memristive memory and we present an analytic approach to predict the expected lifetime distribution of a memristive crossbar.Postprint (published version

Circuit topology and synthesis flow co-design for the development of computational ReRAM

© 2022 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.Emerging memory technologies will play a decisive role in the quest for more energy-efficient computing systems. Computational ReRAM structures based on resistive switching devices (memristors) have been explored for in-memory computations using the resistance of ReRAM cells for storage and for logic I/O representation. Such approach presents three major challenges: the support for a memristor-oriented logic style, the ad-hoc design of memory array driving circuitry for memory and logic operations, and the development of dedicated synthesis tools to instruct the multi-level operations required for the execution of an arbitrary logic function in memory. This work contributes towards the development of an automated design flow for ReRAM-based computational memories, highlighting some important HW-SW co-design considerations. We briefly present a case study concerning a synthesis flow for a nonstateful logic style and the co-design of the underlying 1T1R crossbar array driving circuit. The prototype of the synthesis flow is based on the ABC tool and the Z3 solver. It executes fast owing to the level-by-level mapping of logic gates. Moreover, it delivers a mapping that minimizes the logic function latency through parallel logic operations, while also using the less possible ReRAM cells.Supported by Synopsys, Chile, by the Chilean grants FONDECYT Regular 1221747 and ANID-Basal FB0008, and by the Spanish MCIN/AEI/10.13039/501100011033 grant PID2019-103869RB-C33Peer ReviewedPostprint (author's final draft

Alternative memristor-based interconnect topologies for fast adaptive synchronization of chaotic circuits

© 2020 Elsevier. This manuscript version is made available under the CC-BY-NC-ND 4.0 license http://creativecommons.org/licenses/by-nc-nd/4.0/Resistive switching devices (memristors) constitute an emerging device technology promising for a vari- ety of applications that are currently being studied. In this context, the use of memristors as coupling el- ements of the dynamics of chaotic circuits for adaptive synchronization purposes, was recently proposed and the passive crossbar array was evaluated as target interconnect medium. Nonetheless, memristors may suffer from defects and degradation. Therefore, this work evaluates the impact of memristor switch- ing faults in an adaptive chaotic synchronization scheme, exploring at the same time the fault-tolerance of the crossbar architecture. Moreover, inspired from our observations in the stuck-at-OFF fault analy- sis of the memristive crossbar, some alternative scalable memristive interconnect patterns are suggested, whose performance is found independent of the number of interconnected chaotic circuits, requiring a much smaller number of total memristors than the crossbar array. All simulations are based on an ac- curate physics-based model of a bipolar memristor with filamentary switching mechanism. Based on our results, using the alternative topologies instead of the crossbar array leads to significant savings in the synchronization time that increase with the number of interconnected chaotic units, at the cost of more limited scaling capability and fault-tolerance.This work was supported in part by the Chilean research Grants ANID REDES ETAPA INICIAL 2017 No. REDI170604, ANID FONDECYT INICIACION 11180706, ANID BASAL FB0008, and by the Spanish MINECO and ERDF under Grant TEC2016-75151-C3-2-R.Peer ReviewedPostprint (author's final draft